ASIC/FPGA Design
- Microarchitecture
- RTL design
- Lint check, Synthesis
ASIC verification
- TESTPLAN development
- Building verification environment using system verilog UVM
- Functional coverage and assertions
- Gate level simulation
- Verification closure
Physical Design and Physical verification
- Partitioning
- Floor planning
- Timing closure and ECO implementation
- LVS/DRC checks
Embedded Engineering
- Device drivers
- Board bring up
- Middleware and applications
- Silicon validation
